Data transmission across high-speed chip-to-chip interconnects may take a number of forms. One example illustrating data transmission between high-speed components within a single semiconductor device, or between two devices on a printed circuit board, is represented by the system 10 shown in FIG. 1. In FIG. 1, a transmitter 12 (e.g., a microprocessor) sends data over one or more transmission channels 14a-14c (e.g., copper traces “on-chip” in a semiconductor device or on a printed circuit board) to a receiver 16 (e.g., another microprocessor or memory). As a group, such transmission channels 14a-14c are often referred to as a “data bus,” which allows one or more data signals to be transmitted from one device to another.
Ideally, when a data signal comprising a series of bits (e.g., a bitstream) is sent from a transmitter 12 to a receiver 16 across a channel (e.g., 14a), all of the energy in a transmitted bit is contained within a single time cell, which is often referred to as a unit interval (UI). At the same time, it is hoped that energy from other bits, whether spatially close in time and on the same channel, or spatially close in physical proximity on a neighboring channel (e.g., 14b, 14c), will not affect the bit of interest. Unfortunately, in high-speed applications, this is typically not the case. At least three distinct phenomena result in such interference.
First, pulse dispersion on a given channel, resulting from non-uniform group delay and other bandwidth limitations, results in the spreading of pulse energy beyond the boundaries of the single UI. As a result, energy from bits preceding or following a bit of interest in the bitstream can potentially impact both the amplitude and timing of the bit of interest. This phenomenon is referred to as inter-symbol interference (ISI) and is typically addressed through channel equalization. By either preceding or following the transmission channel with a frequency dependent circuit, whose transfer characteristics are the inverse of the channel characteristics, the original signal behavior may be restored.
The second phenomenon is crosstalk, which is associated with capacitive and inductive coupling between channels on the bus. Crosstalk occurs when transitioning data induces either a voltage (inductive crosstalk) or a current (capacitive crosstalk) on a neighboring line. As is the case with ISI, crosstalk from neighboring channels may alter the amplitude and timing characteristics of a bit of interest on a given channel. Crosstalk is most often addressed with careful channel routing techniques, which may include the placement of additional traces between the channels to provide shielding and to reduce inter-channel coupling.
The third phenomenon that may impact a bit of interest, as it is transmitted across the channel 14, is referred to as simultaneous switching noise (SSN). SSN results from the finite capacity of the power supply network to source and sink current from high-current-draw output drivers. Ideally, the supply network acts as a stable reservoir of current. In real systems, however, the supply network exhibits finite resistance, capacitance, and inductance between the nodes where the drivers connect for power. When a large current is drawn by an output driver during a transition, or during a specific UI, that current generates a voltage across the finite resistance in the associated supply path. This induced voltage may cause voltage level variation in other supply nodes connected to neighboring drivers. Depending upon the sensitivity of the other driving circuits to such supply variation, significant variations in the amplitude and timing of their driven signals may be observed.
It is also possible to observe ringing on the supply due to the inductance and capacitance already mentioned. This ringing may additionally impact the signals being driven, depending upon the sensitivity of the corresponding circuits to that form of supply noise. Thus, in a way similar to crosstalk, SSN, as generated by driving circuits on neighboring channels, may affect a bit of interest on a particular channel.
Because crosstalk occurs as a result of transitions of data on neighboring channels, one way to reduce crosstalk is to reduce the frequency of data transitions. The operation of modifying the data content to reduce transitions, or to achieve any other desired behavior, is referred to as data encoding. One specific form of data encoding that can be used to reduce crosstalk is Data Bus Inversion (DBI).
In principle, DBI includes circuitry that first looks at the relationship between bits to be transmitted across a data bus and then decides (based on an algorithm) if it would be advantageous to invert some or all of the bits prior to transmission. If the bits are inverted, an additional signal (often on another data line), referred to as a DBI bit, is also set to indicate that the bits are inverted. Typically, as shown in FIG. 1, an extra channel 14d is then needed so that the DBI bit may be transmitted in parallel with the bits to identify to the receiving circuitry which sets of data have been inverted. The receiver then uses the DBI bit to return the incoming data to its original state.
One specific DBI algorithm which is used to reduce crosstalk is referred to as the “minimum transitions” algorithm. While there may be variations of this technique, in general the minimum transitions algorithm begins by computing how many bits across the bus will result in a transition during the upcoming cycle. When more than a certain number of transitions are predicted, the DBI circuitry inverts the entire bus, sets the DBI bit to a specified state (high or low depending on the implementation), and drives the inverted data and the DBI bit in parallel across the transmission channel, where the DBI bit is used to de-invert the inverted data prior to use in the receiving system.
One implementation of the minimum transitions technique is shown in FIG. 2A. In brief, the minimum transitions technique comprises comparing the state of an incoming data bit with the state of the previous data bit through an exclusive-OR (XOR) operation, in XOR gate 30. In the example shown in FIG. 2A, two successive bytes of data DIN(0:7) are compared to determine which bits in the data signals have changed. After corresponding bits in the two data signals are compared in an XOR operation and the result is summed, a determination is made as to whether the sum is greater than four (i.e., whether there are at least five transitions from the previous byte of data to the current byte). If the sum is greater than four, the current byte is inverted before it is transmitted, and the DBI bit is transmitted as ‘1.’ Alternatively, if the sum of the data lines in the compared byte is four or less (i.e., there are no more than four transitions from one byte to the next), the data is transmitted unaltered, and the DBI bit is transmitted as ‘0.’
In most cases, as shown in FIG. 2B, the above operations result in no more than three transitions in two successive bytes of data. In any sequence of bytes, no more than four transitions should occur. Example results of the above operations of the computational block 22 are shown in FIG. 2B.
As can be seen in the table titled “Data without Data Bus Inversion,” the number of transitions between two successive non-modified data signals may be derived directly from two successive groups of bits 0-7. For example, from the first data byte ‘00000000’ to the second data byte, ‘11111111’ eight transitions occur and are sent on a channel 14.
Simulated results from using the minimum transitions data bus inversion technique may be seen in the table titled “Data with Data Bus Inversion.” This table shows the result of using the minimum transitions algorithm on the ‘next’ byte of data, in comparison to the current byte of data. When the number of transitions across a non-modified data byte increases to five or more of the data bits (this can be observed by comparing each row of parallel data bits to the left-hand table titled “Data without Data Bus Inversion”), the data byte is inverted and a DBI bit is output as ‘0.’ For example, the second row of data in the table titled “Data without Data Bus Inversion” (‘11111111’) would result in eight bits transitioning from ‘0’ to ‘1’ if the minimum transitions algorithm weren't used after the first row of data bits (‘00000000’) is output. Accordingly, to reduce the number of transitions, the minimum transitions algorithm is used, and the parallel data bits are instead output as ‘00000000’ with the addition of a DBI bit (‘0’). Use of the DBI algorithm results in only a single transition between the first and second rows of data bits, from the change in the DBI bit. As a result of using this technique, any data byte that would have five or more transitions is inverted, which results in no more than four transitions in the modified data byte. Thus, while nine bits are now sent on a channel 14 instead of eight (including the DBI bit), no more than four transitions will occur from one data byte to the next, which helps to reduce SSN.
The minimum transitions technique reduces the number of transitions, and therefore in many input/output circuits topologies reduces the change in current draw at the transmitter 12, which in turn leads to reducing SSN. Additionally, by reducing the number of transitions in transmitted data, capacitive and inductive crosstalk is reduced between parallel signal paths.
The inventor considers the minimum transitions algorithm to have drawbacks. For example, implementation of the minimum transitions algorithm requires that past bit values be known (i.e., stored for at least one cycle) in order to determine if future transitions will occur. There are configurations in which storing past bit values is not possible. Further, in certain systems, use of the minimum transitions algorithm may increase power dissipation. This is particularly true in systems in which signals are referenced through pull-up resistors to a positive power supply. The minimum transitions algorithm may force a signal to remain in state of maximum power dissipation in an effort to minimize the number of transitions.
Another well-known DBI algorithm is referred to as the “minimum zeros” algorithm, which attempts to address issues related to power dissipation. The purpose of this algorithm is to minimize the number of binary zeros transmitted across a data bus. This is helpful in systems wherein the input/output (IO) circuits use pull-up resistors connected to the positive voltage supply as a means for generating an output signal. In such a configuration, maximum current is drawn from the supply (and hence maximum power is dissipated) when a logic ‘0’ is being driven.
The minimum zeros technique is implemented as shown in the system 20 in FIG. 3A, which may be present, for example, in the transmitter 12 shown in FIG. 1. As shown in FIG. 3A, an input data bus 24 inputs a plurality of input data bits DIN(0:7) to computational block 22. The computational block 22 performs operations on the input data bits and outputs the results as output data bits DOUT(0:7) on an output data bus 26 and as a data bus inversion (DBI) bit on DBI line 28, respectively. The output data bus 26 and the DBI line 28 may then lead, for example, to one or more channels 14 in the system 10, shown in FIG. 1.
In brief, the computational block 22 reads a parallel byte of input data and determines whether to invert the input data bus 24. In this example, if half or fewer of the bits of the data byte (i.e., four or fewer bits) comprise ‘high’ (logic ‘1’) values, then all the bits of the data byte are inverted, and the DBI bit is output as ‘0.’ This will guarantee that no more than four transmitted bits, including the DBI bit, are logic ‘0.’ On the other hand, if at least four of the data bits comprise logic ‘1’ values, the output data bits DOUT are assigned the same logic values as the input data bits DIN (i.e., no bits are changed), and the DBI bit on DBI line 28 receives a logic ‘1’ value. Outputting the DBI bit as a logic ‘1’ value assures that no additional power is consumed in transmitting the DBI bit across the channel 14.
Example results of the above-described operations of the computational block 22 are shown in FIG. 3B. The two tables show example bit sequences, as well as the number of ‘1’ and ‘0’ values that result from normal transmission and from the use of the minimum zeros technique. As can be seen in the table titled “Data without Data Bus Inversion,” the number of ‘1’ values or ‘0’ values may be derived directly from the bits 0-7 in a non-modified data byte. For example, from the data byte ‘00000011,’ six ‘0’ values and two ‘1’ values are present on a non-modified data byte that would then be sent on a channel 14. On the other hand, as seen in the table titled “Data with Data Bus Inversion,” when the number of ‘0’ values increases to five or more of the bits in the data byte, the data byte is inverted and a DBI bit is output as ‘0.’ Thus, while nine bits are now sent on the channel 14 instead of eight, no more than four of the nine transmitted bits have logic ‘0’ values, which reduces the number of transmitted ‘0’ bits from five (as seen in the table on the left) to four (as seen in the table on the right).
Although the computational block 22 is shown implemented as pseudocode in FIG. 3A, one skilled in the art will appreciate that the computational block 22 may be implemented in software or in hardware. For example, computational block 22 may be implemented using hardware components such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or combinations of hardware logic elements designed to perform the functionality discussed above.
The use of a DBI algorithm such as either the minimum zeros or the minimum transitions typically requires that an additional bit (i.e., the DBI bit) is included on a data bus or in a transmitted data signal. However, the improvements that result from reducing consumed power, correct signal detection, etc., typically outweigh the negative effects of the resulting decrease in physical space in the integrated circuit or the decrease in bandwidth of the channels 14.
Each of the aforementioned data bus inversion techniques capitalizes on certain characteristics of data signals and the transmission channels on which the data signals are sent. However, in the inventor's opinion, an improved data bus inversion technique would attempt to improve upon these characteristics. The disclosed techniques achieve such results in a manner implemented in a typical computerized system or other circuit package.